The present invention relates to processor-based systems, such as servers and workstations, with I/O (input-output) subsystems or other components or circuits that maintain a FIFO of read and write data.
When an error occurs in a computer system, a useful diagnostic tool is a record of the data transactions that have occurred, in particular the specific read and write data that the I/O subsystem has been transmitting to devices either internal or external to the system. Thus, a history of the inputs to, e.g., a chip or circuit is useful to maintain.
Typically, an I/O subsystem will use a FIFO (first-in, first-out) queue to store read and write data. A particular configuration of FIFO is a circular FIFO, in which all inputs are stored until they are overwritten by subsequent inputs. The present invention will be described in connection with a FIFO in an I/O circuit, but in general the FIFO may be anywhere in the system that queuing of data is required.
Retrieving data from a FIFO involves an inherent latency, and thus the use of a bypass path may be helpful to minimize this latency, by allowing faster access to requested data than if the data is retrieved from the FIFO queue.
A problem with the use of a bypass path is that in conventional systems, inputs provided to a chip or circuit through the bypass path do not become part of the history of transactions that otherwise might occur by passing through the FIFO queue. Accordingly, there has been a trade-off between the ability to speed up data transactions by using a bypass and the ability to debug errors in a system by inspecting suspect transactions.
Accordingly, a system is needed that allows both the lower latency of data access provided by the use of a bypass path, and the advantages of a FIFO that can store the history of data reads and writes in the system.